Advanced Packaging, Not Lithography, Is the Real Chip Bottleneck

Ask a policy analyst where accelerator supply is constrained and you will usually hear about lithography. Ask someone who schedules a fab and you will hear about packaging. The second answer has been the correct one for roughly two years, and the distinction matters because the two constraints relax on very different timelines.

Front-end wafer capacity for leading-edge logic has expanded substantially. The step that has not kept pace is the back end: the process of stacking high-bandwidth memory beside a logic die on an interposer and getting acceptable yield out of the result.

Why the back end became the constraint

A modern accelerator is not one chip. It is a logic die, several stacks of high-bandwidth memory, and a substrate that connects them at a pitch fine enough that the memory bandwidth is usable. That assembly step involves thermal cycling, precise alignment, and a yield penalty applied to components that are already expensive.

Three properties make it hard to scale quickly.

• The equipment is specialised and the vendor list is short. Bonders and inspection tools for fine-pitch interposers come from a handful of suppliers with their own multi-quarter lead times.
• Yield loss compounds. Scrapping an assembly late in the process discards good logic and good memory together, so effective capacity is lower than nameplate capacity by a margin that varies with process maturity.
• Memory supply is coupled. High-bandwidth memory qualification is slow, and the number of stacks per accelerator has been rising, so each unit consumes more of a separately constrained input.

Adding a lithography tool is a capital decision. Adding qualified packaging capacity is a capital decision plus eighteen months of process learning that you cannot buy.

What the numbers look like from the outside

Public disclosure here is thin, which is part of the problem. Foundries report capacity in wafer-equivalent terms that obscure the back end, and packaging subcontractors report revenue rather than qualified units.

The signals that are visible point in one direction. Lead times quoted to large buyers have stayed extended even through periods when wafer starts increased. Substrate suppliers have been running expansion programmes continuously since 2024 without lead times normalising. And the pricing structure has shifted: buyers now commonly contract for packaged units rather than wafers, which is what happens when the scarce step moves downstream.

The forecasting error this creates

Capacity plans written in 2025 generally assumed that accelerator availability would improve as wafer capacity came online, and that per-unit costs would fall accordingly. Teams built serving-cost forecasts on that assumption. As we found reporting on the serving-cost squeeze, several of those forecasts are now being revised upward, because the hardware abundance they priced in has not arrived.

The correction is not dramatic. It is a matter of quarters, not years. But it lands on organisations that committed to product margins based on the earlier curve, and the ones with the least slack are the ones who reserved capacity at fixed prices without a corresponding pricing mechanism on the revenue side.

What would actually change the picture

Three developments would loosen the constraint, in descending order of near-term plausibility.

The first is process maturity at existing packaging lines, which raises effective capacity without new equipment. This is happening steadily and is the main reason supply has improved at all.

The second is architectural: designs that need fewer memory stacks per unit of useful throughput. There is real work here, and it does more for effective supply than a new facility would, because it reduces demand on the coupled input.

The third is new qualified capacity at scale, which is under construction and will matter in 2027 and beyond. Anyone promising relief sooner than that from new facilities is describing an announcement, not a shipment.

For the demand side of this equation, see our reporting on where open-weight models still lose, which shapes how much of the market needs frontier-class hardware at all.